General problems on Xilinx ML605

[Lluis Gesa Bote]

Hi! We are building a laboratory setup basing our project in a Xilinx
ML605 Rev-E, and we want to use Leon3 as our SoC architecture.
We have no experience in FPGA development. We've asked to our experts
from other projects, but still we have some problems that maybe you can
help us to solve:

We are unable to compile grlib-gpl-1.2.1-b4122 nor grlib-gpl-1.2.0-b4121
using ISE 14.3. Following the steps described in the README file, for both
versions we obtain :

Parsing module <rd_bitslip>. Analyzing Verilog file
"/home/fpga/work/GRLOW/Leon3/grlib-gpl-1.2.1-b4122/designs/grlow/mig/user_design/rtl/phy/circ_buffer.v"
into library work Parsing module <circ_buffer>.
ERROR:HDLCompiler:687 -
"/home/fpga/work/GRLOW/Leon3/grlib-gpl-1.2.1-b4122/designs/grlow/mig/user_design/rtl/phy/circ_buffer.v"
Line 89: Illegal redeclaration of module <circ_buffer>.
Verilog file
/home/fpga/work/GRLOW/Leon3/grlib-gpl-1.2.1-b4122/designs/grlow/mig/user_design/rtl/phy/circ_buffer.v
//ignored due to errors

Using ISE 13.2, we can synthesize and generate the bit-file, and FPGA is
programmed without apparently errors, the point is that when grmon is used
next message is shown:


Xilusb: Cable type/rev : 0x3
JTAG chain (2): xc6vlx240t xccace
GRLIB build version: 0
Detected frequency: 0 MHz

and info_sys returns nothing.

With the help of our experts, we've tried to use a tipical vhdl counter
to make a led blink, but did not work. It seems that the clkm signal
generated
by mig instance is not being distributed. The pinout in the ucf is
correct, and we have even tried to invert reset signal, because when
reset button is
kept pushed, the led, surprisingly, blinks.... but with the same results.

So the problem seems that clockm signal isn't well configured.


Finally, we recovered an old LEON3 version (grlib-gpl-1.1.0-b4113), and
with this one, with ISE 13.2, our ML605 can be configured and "hello world"
executed without any problem.

Any suggestion or comment will be welcome.
Thanks!

GRLOW Team
--
Lluís Gesa Boté

Senior R&D Software Engineer
Instituto de Ciencias del Espacio (ICE/CSIC), and
Institut d'Estudis Espacials de Catalunya (IEEC)

Eureka building- UAB Campus.
08193 Bellaterra (Cerdanyola del Vallès) - Barcelona

Tel.: [phone],
Cellular: [phone]
Fax: [phone],
[phone]
Web: http://www.ice.csic.es
http://www.ieec.fcr.es/



------------------------------------

[Jan Andersson]

Hello,

Post by Lluis Gesa Bote
Hi! We are building a laboratory setup basing our project in a Xilinx
ML605 Rev-E, and we want to use Leon3 as our SoC architecture.
We have no experience in FPGA development. We've asked to our experts
from other projects, but still we have some problems that maybe you can
We are unable to compile grlib-gpl-1.2.1-b4122 nor grlib-gpl-1.2.0-b4121
using ISE 14.3. Following the steps described in the README file, for both

1.2.0-b4121 contained errors for the Xilinx flow, in particular for the
ML605 design. It should have been fixed in 1.2.1-b4122 but, of course,
the flow broke again for ML605 at the last minute.

For the flow to work with ML605 please replace
grlib-gpl-1.2.1-b4122/bin/Makefile with the file located at:

http://www.gaisler.com/products/grlib/Makefile

Post by Lluis Gesa Bote
Parsing module <rd_bitslip>. Analyzing Verilog file
"/home/fpga/work/GRLOW/Leon3/grlib-gpl-1.2.1-b4122/designs/grlow/mig/user_design/rtl/phy/circ_buffer.v"
into library work Parsing module <circ_buffer>.
ERROR:HDLCompiler:687 -
"/home/fpga/work/GRLOW/Leon3/grlib-gpl-1.2.1-b4122/designs/grlow/mig/user_design/rtl/phy/circ_buffer.v"
Line 89: Illegal redeclaration of module <circ_buffer>.
Verilog file
/home/fpga/work/GRLOW/Leon3/grlib-gpl-1.2.1-b4122/designs/grlow/mig/user_design/rtl/phy/circ_buffer.v
//ignored due to errors

I cannot reproduce this. Can you provide the full output you get before
this?

Did you run the exact sequence: make mig39 compile_xilinx_verilog_lib
map_xilinx_verilog_lib planAhead ?

Post by Lluis Gesa Bote
Using ISE 13.2, we can synthesize and generate the bit-file, and FPGA is
programmed without apparently errors, the point is that when grmon is used
Xilusb: Cable type/rev : 0x3
JTAG chain (2): xc6vlx240t xccace
GRLIB build version: 0
Detected frequency: 0 MHz
and info_sys returns nothing.

If possible, please test with ISE13.4 instead.

Best regards,
Jan


------------------------------------

[Lluis Gesa Bote]

Thanks Jan!!

We've made the Makefile change but the "cir_buffer" problem is still
present.

Regarding compile_xilinx_verilog_lib and map_xilinx_verilog_lib, we
can't execute them because we have no the "mti_se" simulator:

ERROR:Compxlib - COMPXLIB[sim]: Unable to automatically find executables
for simulator 'mti_se' from the following paths...

I don't know if the xilinxcorelib is strictly needed to be regenerate to
produce the leon3 bit-file, in my ignorance I think that this library
comes precompiled in ISE with its integrated ISIm... well.. I'm a bit
confused about this point... sorry

We will try to use 13.4.

Here the full output for make mig39 and make ise:

***@KoalaIEEC:~/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan$
make mig39

coregen -b mig39.xco -p mig39.cgp
Release 14.3 - Xilinx CORE Generator P.40xd (lin)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
All runtime messages will be recorded in
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/cor
egen.log
INFO:encore:314 - Created non-GUI application for batch mode execution.
WARNING:sim:541 - Could not import file

'/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/mig39.xco' during project migration. A component instance with name
'mig'
already exists within the project. Please check other XCO/XCP files
in the
same directory to resolve any identical 'component_name' values.
WARNING:sim:864 - Failed to create component instance for XCO file

'/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/mig39.xco' during project migration.
INFO:sim:172 - Generating IP...
Resolving generic values...
Finished resolving generic values.
Customizing IP...
Finished Customizing.
INFO:sim:993 - The selected IP does not support an ASY schematic symbol.
INFO:sim:949 - Finished generation of ASY schematic symbol.
Generating metadata file...
Generating ISE project...
XCO file found: mig.xco
XMDF file found: mig_xmdf.tcl
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/controller/arb_mux.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/controller/arb_mux.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/controller/arb_row_col.v -view all -origin_type
created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/controller/arb_row_col.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/controller/arb_select.v -view all -origin_type
created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/controller/arb_select.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/controller/bank_cntrl.v -view all -origin_type
created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/controller/bank_cntrl.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/controller/bank_common.v -view all -origin_type
created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/controller/bank_common.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/controller/bank_compare.v -view all -origin_type
created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/controller/bank_compare.v" into library
work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/controller/bank_mach.v -view all -origin_type
created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/controller/bank_mach.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/controller/bank_queue.v -view all -origin_type
created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/controller/bank_queue.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/controller/bank_state.v -view all -origin_type
created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/controller/bank_state.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/controller/col_mach.v -view all -origin_type
created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/controller/col_mach.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/controller/mc.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/controller/mc.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/controller/rank_cntrl.v -view all -origin_type
created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/controller/rank_cntrl.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/controller/rank_common.v -view all -origin_type
created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/controller/rank_common.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/controller/rank_mach.v -view all -origin_type
created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/controller/rank_mach.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/controller/round_robin_arb.v -view all -origin_type
created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/controller/round_robin_arb.v" into
library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/ecc/ecc_buf.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/ecc/ecc_buf.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/ecc/ecc_dec_fix.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/ecc/ecc_dec_fix.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/ecc/ecc_gen.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/ecc/ecc_gen.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/ecc/ecc_merge_enc.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/ecc/ecc_merge_enc.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/ip_top/clk_ibuf.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/ip_top/clk_ibuf.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/ip_top/ddr2_ddr3_chipscope.v -view all -origin_type
created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/ip_top/ddr2_ddr3_chipscope.v" into
library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/ip_top/infrastructure.v -view all -origin_type
created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/ip_top/infrastructure.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/ip_top/iodelay_ctrl.v -view all -origin_type
created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/ip_top/iodelay_ctrl.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/ip_top/mem_intfc.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/ip_top/mem_intfc.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/ip_top/memc_ui_top.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/ip_top/memc_ui_top.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/ip_top/mig.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/ip_top/mig.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/phy/circ_buffer.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/phy/circ_buffer.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/phy/phy_ck_iob.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/phy/phy_ck_iob.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/phy/phy_clock_io.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/phy/phy_clock_io.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/phy/phy_control_io.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/phy/phy_control_io.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/phy/phy_data_io.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/phy/phy_data_io.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/phy/phy_dly_ctrl.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/phy/phy_dly_ctrl.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/phy/phy_dm_iob.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/phy/phy_dm_iob.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/phy/phy_dq_iob.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/phy/phy_dq_iob.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/phy/phy_dqs_iob.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/phy/phy_dqs_iob.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/phy/phy_init.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/phy/phy_init.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/phy/phy_pd.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/phy/phy_pd.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/phy/phy_pd_top.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/phy/phy_pd_top.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/phy/phy_rdclk_gen.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/phy/phy_rdclk_gen.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/phy/phy_rdctrl_sync.v -view all -origin_type
created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/phy/phy_rdctrl_sync.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/phy/phy_rddata_sync.v -view all -origin_type
created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/phy/phy_rddata_sync.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/phy/phy_rdlvl.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/phy/phy_rdlvl.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/phy/phy_read.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/phy/phy_read.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/phy/phy_top.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/phy/phy_top.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/phy/phy_write.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/phy/phy_write.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/phy/phy_wrlvl.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/phy/phy_wrlvl.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/phy/rd_bitslip.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/phy/rd_bitslip.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/ui/ui_cmd.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/ui/ui_cmd.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/ui/ui_rd_data.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/ui/ui_rd_data.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/ui/ui_top.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/ui/ui_top.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed
successfully./home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/rtl/ui/ui_wr_data.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file

"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan
/tmp/_cg/mig/user_design/rtl/ui/ui_wr_data.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/tmp
/_cg/mig/user_design/par/mig.ucf -view all -origin_type created
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
Please set the new top explicitly by running the "project set top"
command.
To re-calculate the new top automatically, set the "Auto
Implementation Top"
property to true.
Top level has been set to "/mig"
Generating README file...
Generating FLIST file...
INFO:sim:948 - Finished FLIST file generation.
Moving files to output directory...
Finished moving files to output directory
Saved CGP file for project 'mig39'.
patch -p1 < mig_patch.txt
patching file mig/user_design/rtl/ip_top/mig.v
patch -p1 < mig_iodelay_ctrl_patch.txt
patching file mig/user_design/rtl/ip_top/iodelay_ctrl.v
patch -p1 < mig_infrastructure_patch.txt
patching file mig/user_design/rtl/ip_top/infrastructure.v
patch -p1 < mig_ucf_patch.txt
patching file mig/user_design/par/mig.ucf

rm -rf xst
xst -ifn leon3mp.xst
Release 14.3 - xst P.40xd (lin)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
-->
Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.12 secs

-->
Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.12 secs

-->

Reading constraint file leon3mp.xcf.
XCF parsing done.

TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
8.4.5) Cross Clock Domains Report


=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "leon3mp_files.prj"
Input Format : mixed
Synthesis Constraint File : leon3mp.xcf

---- Target Parameters
Target Device : XC6VLX240T-ff1156-1
Output File Name : "leon3mp"

---- Source Options
Automatic FSM Extraction : no
Top Module Name : leon3mp
Verilog Macros : {XSTDUMMY }

---- Target Options
Pack IO Registers into IOBs : true

---- General Options
Optimization Goal : Speed
Optimization Effort : 2
Bus Delimiter : ()

---- Other Options
Cores Search Directories : ../../netlists/xilinx/Virtex4

=========================================================================


=========================================================================
* HDL Parsing *
=========================================================================
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/controller/arb_mux.v"
into library work
Parsing module <arb_mux>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/controller/arb_row_col.v"
into library work
Parsing module <arb_row_col>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/controller/arb_select.v"
into library work
Parsing module <arb_select>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/controller/bank_cntrl.v"
into library work
Parsing module <bank_cntrl>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/controller/bank_common.v"
into library work
Parsing module <bank_common>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/controller/bank_compare.v"
into library work
Parsing module <bank_compare>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/controller/bank_mach.v"
into library work
Parsing module <bank_mach>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/controller/bank_queue.v"
into library work
Parsing module <bank_queue>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/controller/bank_state.v"
into library work
Parsing module <bank_state>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/controller/col_mach.v"
into library work
Parsing module <col_mach>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/controller/mc.v"
into library work
Parsing module <mc>.
INFO:HDLCompiler:693 -
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/controller/mc.v"
Line 202. parameter declaration becomes local in mc with formal
parameter declaration list
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/controller/rank_cntrl.v"
into library work
Parsing module <rank_cntrl>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/controller/rank_common.v"
into library work
Parsing module <rank_common>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/controller/rank_mach.v"
into library work
Parsing module <rank_mach>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/controller/round_robin_arb.v"
into library work
Parsing module <round_robin_arb>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/ecc/ecc_buf.v"
into library work
Parsing module <ecc_buf>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/ecc/ecc_dec_fix.v"
into library work
Parsing module <ecc_dec_fix>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/ecc/ecc_gen.v"
into library work
Parsing module <ecc_gen>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/ecc/ecc_merge_enc.v"
into library work
Parsing module <ecc_merge_enc>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/ip_top/clk_ibuf.v"
into library work
Parsing module <clk_ibuf>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/ip_top/ddr2_ddr3_chipscope.v"
into library work
Parsing module <icon5>.
Parsing module <ila384_8>.
Parsing module <vio_async_in256>.
Parsing module <vio_sync_out32>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/ip_top/infrastructure.v"
into library work
Parsing module <infrastructure>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/ip_top/iodelay_ctrl.v"
into library work
Parsing module <iodelay_ctrl>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/ip_top/mem_intfc.v"
into library work
Parsing module <mem_intfc>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/ip_top/memc_ui_top.v"
into library work
Parsing module <memc_ui_top>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/ip_top/mig.v"
into library work
Parsing module <mig_37>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/phy/circ_buffer.v"
into library work
Parsing module <circ_buffer>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/phy/phy_ck_iob.v"
into library work
Parsing module <phy_ck_iob>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/phy/phy_clock_io.v"
into library work
Parsing module <phy_clock_io>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/phy/phy_control_io.v"
into library work
Parsing module <phy_control_io>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/phy/phy_data_io.v"
into library work
Parsing module <phy_data_io>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/phy/phy_dly_ctrl.v"
into library work
Parsing module <phy_dly_ctrl>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/phy/phy_dm_iob.v"
into library work
Parsing module <phy_dm_iob>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/phy/phy_dq_iob.v"
into library work
Parsing module <phy_dq_iob>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/phy/phy_dqs_iob.v"
into library work
Parsing module <phy_dqs_iob>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/phy/phy_init.v"
into library work
Parsing module <phy_init>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/phy/phy_pd.v"
into library work
Parsing module <phy_pd>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/phy/phy_pd_top.v"
into library work
Parsing module <phy_pd_top>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/phy/phy_rdclk_gen.v"
into library work
Parsing module <phy_rdclk_gen>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/phy/phy_rdctrl_sync.v"
into library work
Parsing module <phy_rdctrl_sync>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/phy/phy_rddata_sync.v"
into library work
Parsing module <phy_rddata_sync>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/phy/phy_rdlvl.v"
into library work
Parsing module <phy_rdlvl>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/phy/phy_read.v"
into library work
Parsing module <phy_read>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/phy/phy_top.v"
into library work
Parsing module <phy_top>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/phy/phy_write.v"
into library work
Parsing module <phy_write>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/phy/phy_wrlvl.v"
into library work
Parsing module <phy_wrlvl>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/phy/rd_bitslip.v"
into library work
Parsing module <rd_bitslip>.
Analyzing Verilog file
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/phy/circ_buffer.v"
into library work
Parsing module <circ_buffer>.
ERROR:HDLCompiler:687 -
"/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/phy/circ_buffer.v"
Line 89: Illegal redeclaration of module <circ_buffer>.
Verilog file
/home/lluis/projects/GRLOW/FPGA/Leon/grlib-gpl-1.2.1-b4122/designs/leon3-jan/mig/user_design/rtl/phy/circ_buffer.v
ignored due to errors
-->


Total memory usage is 110092 kilobytes

Number of errors : 1 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

Post by Jan Andersson
Hello,

Post by Lluis Gesa Bote
Hi! We are building a laboratory setup basing our project in a Xilinx
ML605 Rev-E, and we want to use Leon3 as our SoC architecture.
We have no experience in FPGA development. We've asked to our experts
from other projects, but still we have some problems that maybe you can
We are unable to compile grlib-gpl-1.2.1-b4122 nor

grlib-gpl-1.2.0-b4121

Post by Lluis Gesa Bote
using ISE 14.3. Following the steps described in the README file,

for both
1.2.0-b4121 contained errors for the Xilinx flow, in particular for the
ML605 design. It should have been fixed in 1.2.1-b4122 but, of course,
the flow broke again for ML605 at the last minute.
For the flow to work with ML605 please replace
http://www.gaisler.com/products/grlib/Makefile

Post by Lluis Gesa Bote
Parsing module . Analyzing Verilog file

"/home/fpga/work/GRLOW/Leon3/grlib-gpl-1.2.1-b4122/designs/grlow/mig/user_design/rtl/phy/circ_buffer.v"

Post by Lluis Gesa Bote
into library work Parsing module .
ERROR:HDLCompiler:687 -

"/home/fpga/work/GRLOW/Leon3/grlib-gpl-1.2.1-b4122/designs/grlow/mig/user_design/rtl/phy/circ_buffer.v"

Post by Lluis Gesa Bote
Line 89: Illegal redeclaration of module .
Verilog file

/home/fpga/work/GRLOW/Leon3/grlib-gpl-1.2.1-b4122/designs/grlow/mig/user_design/rtl/phy/circ_buffer.v

Post by Lluis Gesa Bote
//ignored due to errors

I cannot reproduce this. Can you provide the full output you get before
this?
Did you run the exact sequence: make mig39 compile_xilinx_verilog_lib
map_xilinx_verilog_lib planAhead ?

Post by Lluis Gesa Bote
Using ISE 13.2, we can synthesize and generate the bit-file, and

FPGA is

Post by Lluis Gesa Bote
programmed without apparently errors, the point is that when grmon

is used

Post by Lluis Gesa Bote
Xilusb: Cable type/rev : 0x3
JTAG chain (2): xc6vlx240t xccace
GRLIB build version: 0
Detected frequency: 0 MHz
and info_sys returns nothing.

If possible, please test with ISE13.4 instead.
Best regards,
Jan

[Jan Andersson]

Hi,

Post by Lluis Gesa Bote
Thanks Jan!!
We've made the Makefile change but the "cir_buffer" problem is still
present.
Regarding compile_xilinx_verilog_lib and map_xilinx_verilog_lib, we

OK, yes these are not required.
For ISE14 you must use "make planAhead", not "make ise". From the
README.txt:

Simulation and synthesis for ISE-14
-----------------------------------

The design uses the Xilinx MIG memory interface with an AHB-2.0
interface. The MIG source code cannot be distributed due to the
prohibitive Xilinx license, so the MIG must be re-generated with
coregen before simulation and synthesis can be done.

To generate the MIG and install the Xilinx unisim simulation
library, do as follows:

make mig39
make compile_xilinx_verilog_lib
make map_xilinx_verilog_lib

To simulate and run systest.c on the Leon design using the memory
controller from Xilinx use the make targets:

make soft
make vsim-launch

This will ONLY work with ISE-14 installed, and the XILINX variable
properly set in the shell. To build the design, do

make planAhead

and then

make ise-prog-fpga

to program the FPGA.


Best regards,
Jan



------------------------------------

[Lluis Gesa Bote]

ohh.. yes.. I've make a mistake mixing ISE versions, GRLIB versions.. sorry.

The point was that 'make planAhead' without correct Makefile failed with
error:

GRLIB_CONFIG = grlib_config.vhd
testbench.mpf
/bin/sh: @echo: not found
make: *** [planAhead.tcl] Error 127

and then we started to play with ISE versions and GRLIB versions trying
to understand something

Now all seems correct.. with new Makefile, make planAhead runs fine, and
after FPGA programing, grmon runs fine too:


Xilusb: Cable type/rev : 0x3
JTAG chain (2): xc6vlx240t xccace
GRLIB build version: 4122
Detected frequency: 75 MHz

Thanks a lot!

Post by Jan Andersson
Hi,

Post by Lluis Gesa Bote
Thanks Jan!!
We've made the Makefile change but the "cir_buffer" problem is still
present.
Regarding compile_xilinx_verilog_lib and map_xilinx_verilog_lib, we

OK, yes these are not required.
For ISE14 you must use "make planAhead", not "make ise". From the
Simulation and synthesis for ISE-14
-----------------------------------
The design uses the Xilinx MIG memory interface with an AHB-2.0
interface. The MIG source code cannot be distributed due to the
prohibitive Xilinx license, so the MIG must be re-generated with
coregen before simulation and synthesis can be done.
To generate the MIG and install the Xilinx unisim simulation
make mig39
make compile_xilinx_verilog_lib
make map_xilinx_verilog_lib
To simulate and run systest.c on the Leon design using the memory
make soft
make vsim-launch
This will ONLY work with ISE-14 installed, and the XILINX variable
properly set in the shell. To build the design, do
make planAhead
and then
make ise-prog-fpga
to program the FPGA.
Best regards,
Jan

--
Lluís Gesa Boté

Senior R&D Software Engineer
Instituto de Ciencias del Espacio (ICE/CSIC), and
Institut d'Estudis Espacials de Catalunya (IEEC)

Eureka building- UAB Campus.
08193 Bellaterra (Cerdanyola del Vallès) - Barcelona

Tel.: [phone],
Cellular: [phone]
Fax: [phone],
[phone]
Web: http://www.ice.csic.es
http://www.ieec.fcr.es/