how to use the mapping files for SDF generation

[Umair Siddiqui]

Hi,
I generated the SDF of leon3-asic from design compiler, however I got
SDF warnings in modelsim

# ** Warning: (vsim-SDF-3261)
/tmp/umair/grlib-gpl-1.0.22-b4095/designs/leon3-stm65/synopsys/leon3mp.sdf(1069361):
Failed to find matching specify module path.

All these warnings are related to cache memories

verror 3261

reveled that

# vsim Message # 3261:
# No module path in a specify block in the related module instance was
# found to match the SDF construct on the specified line. Verify that
# the SDF file is being applied to the correct design instance and that
# a specify block exists in this module instance and contains the
# appropriate module path. If a COND is being used, verify that the order
# of the condition is the same in the specify block as it is in the
# SDF file.
#

The memory model user guide from ST says that I need to use some mapping files
while writting the SDF

<quote>
For performing STA, a separate mapping file (<library>_pt.map) is
present which is used to write a sdf file. Timing Analysis, should be
performed by reading this sdf in primetime shell.
An example of using a mapping file for writing SDF using a mapping
file is can be

write_sdf -map SPHS.map -output SPHS.sdf

The above command writes out a SDF "SPHS.sdf" using the mapping file
"SPHS.map".
</quote>

now the write_sdf of design compiler doesn't support -map option

could any body please tell me how to proceed .
I tried to write a primetime script to write a new SDF file to use mapping file.

<code>
set link_library "[glob ./*.db] $link_library"
set target_library "[glob ./*.db] $target_library"

# reading the netlist from DC
read_verilog ./synopsys/leon3mp.v

current_design leon3mp
create_clock -name "clka" -period 20 clka

write_sdf -map ../../lib/tech/stm65/mem/SPHS100823.verilog.map
-context verilog -output leon3mp.sdf

report_disable_timing > timing_disable_report
</code>

This is however not working....The warning of type 3262 is removed
instead a new type of SDF warning is generated by modelsim 3259.

# ** Warning: (vsim-SDF-3259) (null)(4905102): Invalid ports for INTERCONNECT.


by

verr 3259 in modelsim i got following message:

vsim Message # 3259:
# The first port instance in an INTERCONNECT entry must be an output
# or bidirectional port. The second port instance must be an input
# or bidirectional port.
# [DOC: OVI Standard Delay Format Specification v3.0 -
# Chapter 3, Section: Delay Definition Entries (page 3-22)]


The design is completely flattened. (previously I was following the
example of virage.tcl in leon3-asic and selectively flattened the
design )


------------------------------------

[Umair Siddiqui]

The confusing thing is that default system test program is running
even with SDF (wrongly) annotated netlist. Even the cache
test is properly passed. If there is problem with my modification of
Dhrystone benchmark (I replace printf with sprintf
and implemented a "fast" printf by modifying
software/leon3/report_device.c and lib/work/debug/grtestmod.vhd)
then why RTL simulation is correctly working?




On Mon, Sep 27, 2010 at 8:16 PM, Umair Siddiqui

Post by Umair Siddiqui
Hi,
I generated the SDF of leon3-asic from design compiler, however I got
SDF warnings in modelsim
# ** Warning: (vsim-SDF-3261)
Failed to find matching specify module path.
All these warnings are related to cache memories
verror 3261
reveled that
# No module path in a specify block in the related module instance was
# found to match the SDF construct on the specified line. Verify that
# the SDF file is being applied to the correct design instance and that
# a specify block exists in this module instance and contains the
# appropriate module path. If a COND is being used, verify that the order
# of the condition is the same in the specify block as it is in the
# SDF file.
#
The memory model user guide from ST says that I need to use some mapping files
while writting the SDF
<quote>
For performing STA, a separate mapping file (<library>_pt.map) is
present which is used to write a sdf file. Timing Analysis, should be
performed by reading this sdf in primetime shell.
An example of using a mapping file for writing SDF using a mapping
file is can be
write_sdf -map SPHS.map -output SPHS.sdf
The above command writes out a SDF "SPHS.sdf" using the mapping file
"SPHS.map".
</quote>
now the write_sdf of design compiler doesn't support -map option
could any body please tell me how to proceed .
I tried to write a primetime script to write a new SDF file to use mapping file.
<code>
set link_library "[glob ./*.db] $link_library"
set target_library "[glob ./*.db] $target_library"
# reading the netlist from DC
read_verilog ./synopsys/leon3mp.v
current_design leon3mp
create_clock -name "clka" -period 20 clka
write_sdf -map ../../lib/tech/stm65/mem/SPHS100823.verilog.map
-context verilog -output leon3mp.sdf
report_disable_timing > timing_disable_report
</code>
This is however not working....The warning of type 3262 is removed
instead a new type of SDF warning is generated by modelsim 3259.
# ** Warning: (vsim-SDF-3259) (null)(4905102): Invalid ports for INTERCONNECT.
by
# The first port instance in an INTERCONNECT entry must be an output
# or bidirectional port. The second port instance must be an input
# or bidirectional port.
# [DOC: OVI Standard Delay Format Specification v3.0 -
# Chapter 3, Section: Delay Definition Entries (page 3-22)]
The design is completely flattened. (previously I was following the
example of virage.tcl in leon3-asic and selectively flattened the
design   )

------------------------------------